3 Ph AC experiments pt. 3

[Glubrecht Dale D <GlubrechtDaleD@JDCORP.DEERE.COM>]

I have been real busy lately, and when that happens I have only so much
time to devote to list issues. But I am back for awhile. IT is deer
slaughter week and most of the workers at this plant are off pumping
lead into the air. So I'll get back to the three phase stuff.
To review:
> -----Original Message-----
> From: Glubrecht Dale D
> Sent: Friday, November 14, 1997 3:45 PM
> To:   Multiple recipients of list EV
> Subject:      3 Ph AC experiments pt. 2
>
>  A six step controller has several main parts. The Waveform generator,
> the High and low side logic, the high and low side isolated drivers,
> the
> low side PWM generator, the current sense and feedback, and a section
> to
> set the current setpoint from the throttle and output the pwm voltage
> and the frequency of the waveform generator.
>
>
> A simple waveform generator is a six state statemachine:
> Forward
> 1  HHHLLL
> 2  HLLLHH
> 3  LLHHHL
>  Reverse is
> 1  HHHLLL
> 2  LLHHHL
> 3  HLLLHH
>
> Just two of the phases are switched to reverse the motor, that could
> be
> done by relays or a more complex state machine. Certain chips can do
> this with the flick of a bit. So just dump the wave form into your
> handiest fpga EDA tool or dust off the old logic books and develop a
> JK
> f/f version.
>
>  Now that you have the basic wave shape you need to be able to vary
> the
> speed of the clock that steps through the states. On an fpga you could
> set up a counter that is compared to a number(speed) and that
> comparator
> generates a bit when the counter =>(speed) The bit generates a reset
> and
> a clock pulse to reset the counter and advance the state machine.
>  On a discrete circuit just use a stupid VCO and divide it down. The
> input voltage  to the VCO will have to be compatible with the output
> of
> an opamp circuit so it can be controlled as an output variable from a
> feedback circuit. The freq will have to be 0-400Hz times 6 (states)
>
        There are variations of the 6 step. They usually involve
narrowing the pulse between top and bottom transitions (switching from
high side to the low side of the three phase bridge.) This gives a wave
form that looks very good on an O-scope. It is not necessary but it does
improve efficiency.

        The original simple six step idea just had provisions for dead
time (time lag between the top switch turning off and the bottom turning
on) but not for harmonic compensation. The new wave form:
        HHFLLF
        LFHHFL
        FLLFHH

        OR
        HHHHFFLLLLFF
        LLFFHHHHFFLL
        FFLLLLFFHHHH

        In either case the circuit has six outputs: one H/L and one
F/notF. The original state machine just needs three more outputs, one
for each phase, that come on during the "F" states. That is just more
combinational logic in a FPGA or discretes. The float output just has to
disable the driver stage of the particular phase or the output to the
driver.

        Now that you have a waveform that looks proper it needs to have
the amplitude adjusted. Now all you need is one pwm generator that is
voltage controlled. If you are using an FPGA it is simple. Take your
clock and divide it down to your PWM frequency times the number of
discrete pwm levels you want. ex. 1M / (15000 /256) That new clock freq
runs a 8bit counter(256 levels). The output of the counter is compared
to a voltage word. When the voltage word<= the counter word a bit goes
low.  That output bit is the pwm signal. The voltage word is controlled
by the frequency/ voltage  control loop.

        If you are doing a discrete implementation I would suggest
looking at the MC33035  Motorola datasheet. IT has a pwm generator that
is perfect for this. The inputs can be taken right from your waveform
generator except the outputs have to be "ANDed" with the F/notF outputs
of the phase before they go to the high or low side driver. If you want
to use opamps for all of this then do the triangle wave that is compared
to a voltage type of PWM.

        The PWM could just drive the lower switches. That's what the
MC33035 chip does and it makes the logic a little bit simpler. The drive
could also be simplified if, for a low powered unit, you used PNP BJ
transistors. Rather than "AND" pwm with six channels in a FPGA you just
"AND" the three lowside phases with the pwm. "ANDing" all six channels
or low and high side of each phase with the PWM might make REGEN act
better but I have not tried this yet. There is more than one way to
drive a full three phase bridge with PWM.

        Another drive system is to use three half bridge drivers or two
and 1/2 full bridge drivers that the top and bottom are controlled
through one pin. For low voltage systems use a Harris 4082. For higher
voltage systems IR has a similar product like the IR2104. This only
handles a half bridge so you need three. This has a set dead time but
the deadtime can be increased with a little filter to give the
squarewave a trapezoidal shape. Now this method gives you dead time
every pwm cycle. When you switch from high side to low side for just
that phase you have to enable or switch from the non inverted output of
the pwm to the inverted output of your PWM. The PWM has to be limited to
greater than 50% duty cycle. The effect is that at low amplitude AC and
during the hi time the top transistor is on a bit more than when at the
low time. Like a 60% duty cycle (40%off) voltage is 60V on 100V buss.
When the low side is active and the same amplitude is dialed in you get
a 40% duty cycle (60%off). Remember I am measuring the duty cycle at the
input to the driver not at the switches. For high amplitudes during the
high side the duty cycle is 99 - 100% (not recommended with these
drivers unless you design it in.). When the low side has its turn the
duty cycle is 0-1% even though your PWM generator is still at 99-100%
you are just using the inverted output now.

        To implement the float state you have to take your float output
(Float= active low) and feed it to the SD pin on the IR2104. This will
shut that phase down for the duration of the float state.

        Now we have the waveform generator, PWM generator, the driver, a
couple of chip options for incorporating one or more of the previously
mentioned functions and some loose ends dangling in bit limbo. After a
period of a few days I will get into the frequency/voltage/ current
control loop and tie the system together. Then I will start on the power
section.
        Questions?
        Enjoy Thanksgiving
*****************************
Dale Glubrecht
My Porsche Would Be Zero Emission
But My Tires Keep Smoking...
John Deere WC&CE div.
mx10273@deere.com
*****************************

3 Ph AC experiments pt. 3